pl611s-19 0.5khz- 12 5mhz, mhz to khz programmable clock tm micrel inc. ? 2180 fortune drive ? san jose, ca 951 31 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 7/8/08 page 1 features ? designed for very low-power applications ? input frequency, ac coupled : o reference input: 1mhz to 125mhz o accepts >0.1v input signal voltage ? output frequency up to 12 5mhz lv cmos o < 65mhz @ 1.8v operation o < 90 mhz @ 2.5v operation o < 12 5mhz @ 3.3v operation ? one programmable input pin can be configured as power down (pdb) input, output enable (oe), or frequency selection switching input ? disabled outputs active low ? low current consumption: o <1.0ma with 27mhz & 32khz outputs o <5a when pdb is activated ? single 1.8v ~ 3.3v, 10% power supply ? operating temperature range from - 40 ? c to 85 ? c ? available in 6-pin dfn, and sot23 green/rohs compliant packages description the pl611s-19 is a low-cost general purpose frequency synthesizer and a member of q uick turn clock (qtc) family. pl611s-19 offers the versatility of using a single reference clock input and produci ng up to two (khz or mhz) system clock outputs. designed for low-power applications with very stringent space requirement, pl611s- 19 consumes ~1.0ma, while producing 2 distinct outputs of 27mhz and 32khz. the power down feature of pl611s- 19 , when activated, allows the ic to consume less than 5a of power. the pl611s- 19 fits in a small dfn or sot23 package. cascading of the pl611s- 19 with other programmabl e clocks allow generating system level clocking requirements, thereby reducing the overall system implementation cost. in addition, one programmable input pin can be configured as power down (pdb) input, output enable (oe), or frequency switching (fsel) . the clk1 output can be programmed as f ref or clk0. pin configurations block diagram phase detector charge pump loop filter vco fin r-counter (5-bit) f vco = f ref * (2 * m/r) f out = f vco / (2 * p) clk0 f ref oe, pdb, fsel m-counter (8-bit) programmable function p-counter (14-bit) /2 programming logic clk1 1 2 3 4 5 6 clk1 gnd fin vdd oe , pdb , fsel clk0 dfn-6l (2. 0 x 1. 3 x 0.6 mm ) sot 23 -6l (3. 0 x 3. 0 x 1. 35 mm ) fin oe , pdb , fsel gnd vdd clk0 clk1 pl611s-19 12 3 65 4 pl611s-19 downloaded from: http:///
pl611s-19 0.5khz- 12 5mhz, mhz to khz programmable clock tm micrel inc. ? 2180 fortune drive ? san jose, ca 951 31 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 7/8/08 page 2 key programming param eters clk output frequency output drive strength programmable input f out = f ref * m / (r * p) where m = 8 bit r = 5 bit p = 14 bit clk0 = f out , f ref or f ref / (2*p) clk1 = f ref or clk0 two optional drive strengths to choose from: ? low: 4ma ? std: 8ma (default) one output pin can be configured as: ? oe - input ? fsel - input ? pdb C input pin descriptions name pin assignment type description dfn pin# sc70 pin# sot pin # clk1 2 1 1 i/o programmable clock output gnd 3 5 2 p gnd connection fin 1 3 3 i reference input pin oe, pdb, fsel 6 2 4 o this programmable input pin can be configured as an output enable (oe) input, power down input (pdb) or on -the -fly frequency switching selector (fsel). this pin has an internal pull up resistor for oe, pdb & fsel. vdd 5 4 5 p vdd connection clk0 4 6 6 o programmable clock output oe and pdb function description oe pdb osc. pll clk0 clk1 when clk1=f ref when clk1=clk0 1(default) n/a on on on on on 0 n/a on off active low on active low n/a 1(default) on on on on on n/a 0 off off active low active low active low downloaded from: http:///
pl611s-19 0.5khz- 12 5mhz, mhz to khz programmable clock tm micrel inc. ? 2180 fortune drive ? san jose, ca 951 31 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 7/8/08 page 3 functional description pl611s- 19 is a highly featured, very flexible, advanced prog rammable pll design for high performance, low - power, small form-factor applications. the pl611s - 19 accepts a reference clock input of 1mhz to 125mhz and is capable of producing two outputs from 0.5khz to 12 5mhz. this flexible design allows the pl611s- 19 to deliver any pll generated frequency, f ref (ref cl oc k) frequency or f ref /(2*p) to clk0 and/or clk1. some of the design features of the pl611s- 19 are mentioned below: pll programming the pll in the pl611s- 19 is fully programmable. the pll is equipped with an 5-bit input frequency divider (r-counter), and an 8-bit vco frequency feedback loop divider (m-counter). the output of the pll is transferred to a 14-bit post vco divider (p -counter). the output frequency is determined by the following formula [f out = f ref * m / (r * p) ]. clock output (clk0) the output of clk0 can be configured as the pll output (f v co /(2*p)), f ref (ref clk frequency) output, or f ref /(2*p) output. the output drive level can b e programmed to low drive (4ma) or standard drive (8ma). the maximum output frequency is 125mhz @ 3.3v, 90mhz @ 2.5v or 65mhz @ 1.8v. clock output (clk1) the output of clk1 can be configured as: f ref C reference (ref clock) frequency clk0 C pll derived frequency the output drive level can be programmed to low drive (4ma) or standard drive (8ma). the maximum output frequency is 12 5mhz @ 3.3v, 90mhz @ 2.5v or 65mhz @ 1.8v . programmable input pin (oe/pdb/fsel) the pl611s- 19 provides one programmable i/o pin which can be configured as one of the following functions: output enable (oe) the output enable feature allows the user to enable and disable the clk0 output by toggling the oe pin. using the oe function the clk1 clock output will remain on when programmed as fref and will disable when programmed to clk0 (see oe and pdb function description on page 2). the oe pin incorporates a 60k? pull up resistor giving a defau lt condition of logic 1 (enabled). power-down control (pdb) the power down (pdb) feature allows the user to put the pl611s- 19 into sleep mode. when activated (logic 0), pdb disables the pll, the oscillator circuitry, counters, and all other active circuitry . in power down mode the ic consumes <5a of power. the pdb pin incorporates a pull up resistor giving a default condition of logic 1 (enabled). frequency select (fsel) the frequency select (fsel) feature allows the pl611s- 19 to switch between two pre-programmed outputs allowing the device on the fly frequency switch ing. the fsel pin incorporates a 60k? pull up resistor giving a default condition of logic 1. downloaded from: http:///
pl611s-19 0.5khz- 12 5mhz, mhz to khz programmable clock tm micrel inc. ? 2180 fortune drive ? san jose, ca 951 31 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 7/8/08 page 4 electrical specifications absolute maximum ratings parameters symbol min. max. units supply voltage range v dd -0.5 7 v input voltage range v i -0.5 v dd +0.5 v output voltage range v o -0.5 v dd +0.5 v soldering temperature (green package) 260 ? c data retention @ 85 ? c 10 year storage temperature t s - 65 150 ? c ambient operating temperature* - 40 85 ? c exposure of the device under conditions beyond the limits specified by maximum ratings for extended pe riods may cause permanent damage to the device and affect product reliability. these conditions r epresent a stress rating only, and functional opera tions of the device at these or any other condition s abov e the operational limits noted in this specification is not implied. *operating temperature is guaranteed by design. par ts are tested to commercial grade only. ac specifications parameters conditions min. typ. max. units input (fin) frequency @ v dd =3.3v 1 125 mhz @ v dd =2.5v 90 @ v dd =1.8v 65 input (fin) signal amplitude internally ac coupled (high frequency) 0. 8 v dd vpp input (fin) signal amplitude internally ac coupled (low frequency) 3.3v < 50mhz, 2.5v < 40mhz, 1.8v < 15mhz 0.1 v dd vpp output frequency @ v dd =3.3v 0.5khz 12 5 mhz @ v dd =2.5v 90 mhz @ v dd =1.8v 65 mhz settling time at power-up (after v dd increases over 90% of operating v dd ) 2 ms output enable time oe function; ta=25o c, 15pf load 10 ns pdb function; ta=25o c, 15pf load 2 ms output rise time 15pf load, 10/90% v dd , std drive, 3.3v 2.0 3.0 ns output fall time 15pf load, 90/10% v dd , std drive, 3.3v 2.0 3.0 ns duty cycle pll enabled, @ v dd /2 45 50 55 % period jitter,pk- to -pk* (10 k samples measured) capacitive decoupling between v dd and gnd. 70 ps * note: jitter perform ance depends on the programmi ng parameters. downloaded from: http:///
pl611s-19 0.5khz- 12 5mhz, mhz to khz programmable clock tm micrel inc. ? 2180 fortune drive ? san jose, ca 951 31 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 7/8/08 page 5 dc specifications parameters symbol conditions min. typ. max. units supply current, dynamic i dd @ v dd =3.3v, 27mhz, load=15pf 4.0 ma supply current, dynamic i dd @ v dd =2.5v, 27mhz, load=10pf 2.7 ma supply current, dynamic i dd @ v dd =1.8v, 27mhz, load=5pf 1.1 ma pll off: supply current, dynamic i dd @ v dd =3.3v, 32 khz , load=15pf 0.6 ma pll off: supply current, dynamic i dd @ v dd =2.5v, 32k hz, load=15 pf 0.5 ma pll off: supply current, dynamic i dd @ v dd =1.8v, 32 khz , load=1 5pf 0. 2 ma supply current, dynamic i dd when pdb=0 5 a operating voltage v dd 1.62 3.63 v power supply ramp t pu time for v dd to reach 90% v dd . power ramp must be monotonic. 100 ms output low voltage v ol i ol = +4ma 0.4 v output high voltage v oh i oh = -4ma v dd C 0.4 v output current, low drive i osd v ol = 0.4v, v oh = 2.4v 4 ma output current, standard drive i osd v ol = 0.4v, v oh = 2.4v 8 ma downloaded from: http:///
pl611s-19 0.5khz- 12 5mhz, mhz to khz programmable clock tm micrel inc. ? 2180 fortune drive ? san jose, ca 951 31 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 7/8/08 page 6 pcb layout considerations for performance optimization the following guidelines are to assist you with a p erformance optimized pcb design: - keep all the pcb traces to pl611s-19 as short as possible, as well as keeping all other traces as fa r away from it as possible. - when a reference input clock is generated from a crystal, place the pl611s-19 fin as close as possible to the xout crystal pin. this will redu ce the cross-talk between the reference input and the other signals. - place a 0.01f~0.1f decoupling capacitor between vdd and gnd, on the component side of the pcb, close to the vdd pin. it is not recommended to place this component on the backside of the pcb. going through vias will reduc e the signal integrity, causing additional jitte r and phase noise. - it is highly recommended to keep the vdd and gnd traces as short as possible. - when connecting long traces (> 1 inch) to a lv cmos output, it is important to design the traces as a transmission line or stripline, to avoid reflections or ringing. in this case, the lv cmos output needs to be matched to the trace impedance. usually striplines are designed for 50? impedance and lv cmos outputs usually have lower than 50? impedance so matching can be achieved by adding a resistor in series with the lv cmos output pin to the stripline trace. - please contact micrel for the application note on how to design outputs driving long traces or for additional layout assistance. dfn-6l evaluation board downloaded from: http:///
pl611s-19 0.5khz- 12 5mhz, mhz to khz programmable clock tm micrel inc. ? 2180 fortune drive ? san jose, ca 951 31 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 7/8/08 page 7 d e bottom view d1 b e e1 l a3 a a1 pin 6 id chamfer pin 1 dot top view package drawings (green package com pliant) sot23- 6l dfn- 6l symbol dimension in mm min. max. a 1.05 1.35 a1 0.05 0.15 a2 1.00 1.20 b 0.30 0.50 c 0.08 0.20 d 2.80 3.00 e 1.50 1. 70 h 2.60 3.00 l 0.35 0.55 e 0.95 bsc symbol dimension in mm min. max. a 0.50 0.60 a1 0.00 0.05 a3 0.152 0.152 b 0.15 0.25 e 0.40bsc d 1.25 1.35 e 1.95 2.05 d1 0.75 0.85 e1 0.95 1.05 l 0.20 0.30 c l a2 e h d a1 e b a pin 1 dot downloaded from: http:///
pl611s-19 0.5khz- 12 5mhz, mhz to khz programmable clock tm micrel inc. ? 2180 fortune drive ? san jose, ca 951 31 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 7/8/08 page 8 ordering inform ation (green package com pliant) for part ordering, please contact our sales departmen t: 2180 fortune drive, san jose, ca 95131, usa tel: (408) 944-0800 fax: (408) 474-1000 part number the order number for this device is a combination of the follow ing: part number, package type and operating temperature range pl 611 s- 19 - xx x x x x * micrel will assign a unique 3-digit id code for each approv ed programmed part number. part /order number marking ? package option pl611s- 19 - xxx gc-r xxx 6-pin dfn (tape and reel) pl611s- 19 - xxx tc -r 19xxx 6-pin sot23 (tape and reel) ? note: xxx designates marking identifier that, at times, could be independent of the part number. micrel inc., reserves the right to make changes in its products or specifications, or both at any time wit hout notice. the information furnished by micrel is believed to be accurate and reliable. however, micrel makes no guarantee or warranty concerning the accuracy of said information and shall not be re sponsible for any loss or damage of whatever nature res ulting from the use of, or reliance upon this product. life support policy : micrels products are not authorized for use as c ritical components in life support devices or syste ms without the express written approval of the president of micrel inc. part number temperature c=commercial (0c to 70c) i = industrial (-40c to 85c) package type g=dfn- 6l t=sot- 6l 3 digit id code * (will be assigned at programming time) r=tape and reel downloaded from: http:///
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